Complexity levels of electronic device testing vary tremendously. Simple device testing may be performed with manual low-volume/low-complexity evaluations using perhaps an oscilloscope and voltmeter. Medium-scale testing may employ personal computer-based evaluation systems. Large-scale/high-complexity evaluations typically employ automated test equipment (ATE).
Manual and personal computer-based testing are typically applied when testing discrete devices, specific components of an integrated circuit, or portions of a printed circuit board. In contrast, ATE testing is used to test functionality of a plurality of complex integrated circuits (ICs) such as memory circuits or hundreds of dice on a wafer prior to sawing and packaging.
FIG. 1 shows a block diagram of a prior art automated test system 100. The test system 100 includes a test system controller 101, a test head 105, and a test prober 107. The test system controller 101 is frequently a microprocessor-based computer and is electrically connected to the test head 105 by a communication cable 103. The test prober 107 includes a stage 109 on which a semiconductor wafer 111 may be mounted and a probe card 113 for evaluating devices under test (DUTs) on the semiconductor wafer 111. The stage 109 is movable to contact the wafer 111 with a plurality of test probes 115 on the probe card 113. The probe card 113 communicates with the test head 105 through a plurality of channel communications cables 117.
In operation, the test system controller 101 generates test data which are transmitted through the communication cable 103 to the test head 105. The test head in turn transmits the test data to the probe card 113 through the plurality of communications cables 117. The probe card then uses these data to probe DUTs (not shown explicitly) on the wafer 111 through the plurality of test probes 115. Test results are then provided from the DUTs on the wafer 111 back through the probe card 113 to the test head 105 for transmission back to the test system controller 101. Once testing is completed and known good dice are identified, the wafer 111 is diced.
Test data provided from the test system controller 101 are divided into individual test channels provided through the communication cable 103 and separated in the test head 105 so that each channel is carried to a separate one of the plurality of test probes 115. Channels from the test head 105 are linked by the channel communications cables 117 to the probe card 113. The probe card 113 then links each channel to a separate one of the plurality of test probes 115.
Typical probe card assemblies, such as the probe card 113 of FIG. 1, are currently manufactured by various companies. However, typical contemporary types of probe card assemblies have several limitations. For example, in using a low-temperature co-fired ceramic (LTCC) substrate or a high-temperature co-fired ceramic (HTCC) substrate thick film process, a maximum size of the ceramic substrate is typically 150 mm (6 inches) square. However, the size of the wafer for typical memory devices is currently 300 mm (approximately 12 inches) diameter with 450 mm (approximately 18 inches) wafer diameters following shortly. Hence, several HTCC or LTCC substrates need to be tiled together to cover the surface of the wafer in a single pass. For example, four ceramic tiles are needed merely to cover the area of a single 300 mm wafer.
Tiling of HTCC or LTCC ceramic substrates creates a number of mechanical challenges. First, each of the plurality of substrates needs to be coplanar with each of the other substrates. Additionally, each of the four ceramic tiles needs to be individually aligned to DUTs on a wafer. This alignment necessitates a small gap to be placed between each of the tiles. As a result of the small gap, bond pads located in these same relative areas of the wafer cannot be contacted easily. Further, each of the tiles has a “keep-out” area around the perimeter of each tile. The keep-out area is required for handling during processing and is roughly 2 mm from each edge.
Other limitations include expensive processing requirements. For example, to laminate each subsequent layer, both the LTCC and HTCC substrates need to be co-fired after each layer is applied. Typical LTCC and HTCC substrates have up to 24 layers each and thus need to be co-fired 24 times, providing for an expensive process. Also, since the LTCC and HTCC substrates use thick film processes for their fabrication, a typical photolithographic process which uses a wet chemical etch can only define 25 μm to 50 μm (1 mil to 2 mil) wide traces. The large trace widths greatly limit the routing density available within the substrate.
Since the HTCC substrate is fired at over 900° C., traces are typically made of tungsten (W) to withstand the heat. However, tungsten is highly resistive (having approximately only 20% the conductivity of copper (Cu)) and therefore degrades the signal fidelity of the ATE system. The LTCC substrate is fired at 300° C. and the traces are usually made of a gold-based alloy which is also fairly resistive (approximately 80% the conductivity of Cu), although less resistive than tungsten.
In another example of limitations of contemporary substrates, the HTCC substrate from one manufacturer, for instance, features a modified wire bonder to make a contact element that is ball bonded to the HTCC substrate. The other end of the wire bond contacts the wafer. However, an overall vertical height of the wire bond is only 1 mm. The vertical height limits an available thickness of any bypass capacitors that can be mounted on the wafer side of the HTCC substrate. Most high frequency capacitors are made of COG-grade materials and are approximately 1.0 mm thick. Hence, a lower grade capacitor material, such as X7R or Y5V (known in the art), must be used. The lower grade capacitors are thinner but have a bandwidth limitation of about 500 MHz. The frequency of the current generation of DRAM is 533 MHz, so these lower grade materials may work fairly adequately. However, the next generations of DRAM will run at 800 MHz and 1.066 GHz, respectively. Therefore, these lower grade capacitance materials will no longer be adequate.
The LTCC substrate from one prior art manufacturer features a MEMs-based contact that has a vertical height of roughly 0.3 mm (i.e., 300 μm). The vertical height in this case prohibits bypass capacitors from being mounted on the wafer side of the ceramic substrate at all. The MEMs-based technology requires any bypass capacitors to be placed on the printed circuit board (PCB). The PCB is several millimeters away from the DUT and thus creates added inductance and other parasitic reactance levels. The added inductance alone limits the performance of the bypass capacitors to less than 100 MHz and excludes such probe cards from testing contemporary DRAM devices running at 533 MHz.
Therefore, what is needed is a means to simply and economically test DUTs contained on large-area substrates in high speed applications, preferably with a single touchdown onto the substrate.